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1 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs WED3C7410E16M-XBHX july 2004 rev. 0 preliminary* 7410e risc microprocessor hitce? multichip package overview the wedc 7410e/ssram multichip package is targeted for high performance, space sensitive, low power systems and supports the following power management features: doze, nap, sleep and dynamic power management. the WED3C7410E16M-XBHX multichip package consists of: 7410e altivec? risc processor dedicated 2mb ssram l2 cache, con? gured as 256kx72 21mmx25mm, 255 hitce? ball grid array (cbga) core frequency = 450 or 400mhz @ 1.8v maximum l2 cache frequency = 200mhz maximum 60x bus frequency = 100mhz * this product is under development, is not quali? ed or characterized and is subject to change without notice. the WED3C7410E16M-XBHX is offered in commercial (0c to +70c), industrial (-40c to +85c) and military (-55c to +125c) temperature ranges and is well suited for embedded applications such as missiles, aerospace, ? ight computers, ? re control systems and rugged critical systems. features footprint compatible with wed3c7410e16m-xbx, wed3c7558m-xbx and wed3c750a8m-200bx implementation of altivec ? technology instruction set optional, high-bandwidth mpx bus interface hitce? interposer for tce compatibility to laminate substrates for increased board level reliability available with eutectic or high lead solder balls figure 1 C multi-chip package diagram altivec? is a trademark of motorola inc. hitce? is a trademark of kyocera corp.
2 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs WED3C7410E16M-XBHX july 2004 rev. 0 preliminary reservation station reservation station fetcher dispatch unit reservation station vector permute unit vscr vector alu vsiu vciu vfpu reservation station vr file 6 rename buffers reservation station interger unit 1 . . + x interger unit 2 . . gpr file 6 rename buffers . . fpr file 6 rename buffers . . system register unit vector to u c h queue reservation station floating-point unit reservation station (2 entry) load/store unit (ea calculation) finished stores complete stores l1 operations load fold queue + + . . + x fpscr additional features time base counter/decrementer clock muliplier jtag/cop interface thermal/power management performance monitor instruction queue (6 word) completion queue (8 entry) completion unit branch processing unit btic (64 entry) bht (512 entry) lr ctr instruction mmu srs (shadow) 128-entry dtlb ibat array data mmu srs (original) 128-entry dtlb dbat array ta g s 32-kbyte i cache ta g s 32-kbyte i cache ability to complete up to two instructions per clock l2 data transaction queue l2 controller l2 tags l2cr l2pmcr l2 miss l2 castout data transaction queue bus interface unit data reload buffer instruction reload buffer instruction reload table data reload ta b l e memory subsystem ssram ssram 19-bit l2 address bus 64- 32-bit l2 data bus 64-bit data bus 32-bit address bus 32-bit 32-bit 32-bit 64-bit 64-bit 128-bit 128-bit ea pa 128-bit (4 instructions) figure 2 C block diagram
3 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs WED3C7410E16M-XBHX july 2004 rev. 0 preliminary figure 3 C block diagram, l2 interconnect l2pin_data l2pin_data l2pin_data l2pin_data l2 clk_out a l2we# l2ce# a 0-17 l2clk_out b l2pin_data l2pin_data l2pin_data l2pin_data l2zz mp 7410e dqa dqb dqc dqd k sgw# se1# sa 0-17 sa 0-17 sgw# se1# k dqa dqb dqc dqd ssram 1 ssram 2 ft# sbd# sbc# sbb# sba# sw# adsp# adv# se2 adsc# se3# lbo# g# ft# sbd# sbc# sbb# sba# sw# adsp# adv# se2 adsc# se3# lbo# g# l2vdd l2vdd l2dp0-3 dp0-3 l2dp4-7 dp0-3 zz zz u2 u1
4 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs WED3C7410E16M-XBHX july 2004 rev. 0 preliminary figure 5 C pin assignments ball assignments of the 255 cbga package as viewed from the top surface. side pro? le of the cbga package to indicate the direction of the top surface view.
5 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs WED3C7410E16M-XBHX july 2004 rev. 0 preliminary package pinout listing signal name pin number active i/o 1.8v (7) 2.5v (7) 3.3v (7) a[0-31] c16, e4, d13, f2, d14, g1, d15, e2, d16, d4, e13, g2, e15, h1, e16, h2, f13, j1, f14, j2, f15, h3, f16, f4, g13, k1, g15, k2, h16, m1, j15, p1 high i/o aack# l2 low input abb#/amono# (8) k4 low output ap[0-3] c1, b4, b3, b2 high i/o artry# j4 low i/o av cc a10 input 1.8v 1.8v 1.8v bg# l1 low input br# b6 low output bvsel (4, 6) b1 high input gnd hreset# ov cc chk# (5, 6, 13) c6 low input ci# e1 low i/o ckstp_in# d8 low input ckstp_out# a6 low ouput clk_out d7 high output dbb#/dmono (8) j14 low output dbg# n1 low input dbwo#/dti[0] g4 low input dh[0-31] p14, t16, r15, t15, r13, r12, p11, n11, r11, t12, t11, r10, p9, n9, t10, r9, t9, p8, n8, r8, t8, n7, r7, t7, p6, n6, r6, t6, r5, n5, t5, t4 high i/o dl[0-31] k13, k15, k16, l16, l15, l13, l14, m16, m15, m13, n16, n15, n13, n14, p16, p15, r16, r14, t14, n10, p13, n12, t13, p3, n3, n4, r3, t1, t2, p4, t3, r4 high i/o dp[0-7] m2, l3, n2, l4, r1, p2, m4, r2 high i/o drdy# (5, 9, 12) d5 low output dti 1-2 (9, 11) g16, h15 high input emode# (10, 11) c4 low input gbl# f1 low i/o gnd c5, c12, e3, e6, e8, e9, e11, e14, f3, f5, f7, f10, f12, g6, g8, g9, g11, h5, h7, h10, h12, j5, j7, j10, j12, k6, k8, k9, k11, l5, l7, l10, l12, m3, m6, m8, m9, m11, m14, p5, p12 gnd gnd gnd hit# (5) (12) a3 low output hreset# a7 low input int# b15 low input l1_tstclk (1) d11 high input l2_tstclk (1) d12 high input l2av cc l11 input 1.8v 1.8v 1.8v l2v cc (5) (7) a2, b8, c3, d6, j16 input 3.3v 3.3v 3.3v l2ov cc e10, e12, m12, g12, g14, k12, k14 input 2.5v n/a l2vsel (3, 6) b5 high input * hreset# n/a lssd_mode# (1) b10 low input 3.3v mcp# c13 low input nc (no-connect) b7, c8 ov cc (2) c7, e5, g3, g5, k3, k5, p7, p10, e7, m5, m7, m10 input 1.8v 2.5v 3.3v pll_cfg[0-3] a8, b9, a9, d9 high input qack# d3 low input qreq# j3 low output rsrv# d1 low output shd0-1# (5) (14) a4, a5 low i/o smi# a16 low input sreset# b14 low input
6 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs WED3C7410E16M-XBHX july 2004 rev. 0 preliminary signal name pin number active i/o 1.8v (7) 2.5v (7) 3.3v (7) sysclk c9 input ta# h14 low input tben c2 high input tbst# a14 low output tck c11 high input tdi (6) a11 high input tdo a12 high output tea# h13 low input tms (6) b11 high input trst# (6) c10 low input ts# j13 low i/o tsiz[0-2] a13, d10, b12 high output tt[0-4] b13, a15, b16, c14, c15 high i/o v cc (2) f6, f8, f9, f11, g7, g10, h4, h6, h8, h9, h11, j6, j8, j9, j11, k7, k10, l6, l8, l9 input 1.8v 1.8v 1.8v wt# d2 low i/o package pinout listing (continued) notes: 1. these are test signals for factory use only and must be pulled up to ov cc for normal machine operation. 2. ov cc inputs supply power to the i/o drivers and v cc inputs supply power to the processor core. 3. to allow future l2 cache i/o interface voltage changes. 4. to allow processor bus i/0 voltage changes, provide the option to connect bvsel to hreset# (selects 2.5v interface) or to gnd (selects 1.8v interface) or to ov cc (selects 3.3v interface). 5. uses one of 9 existing no-connects in wedcs wed3c755a8m-300bx. 6. internal pull up on die. 7. ov cc supplies power to the processor bus, jtag, and all control signals except the l2 cache controls (l2ce, l2we, and l2zz); l2ov cc supplies power to the l2 cache i/o interface (l2addr (0-18], l2data (0-63), l2dp{0-7] and l2sync-out) and the l2 control signals; l2av cc supplies power to the ssram core memory; and v cc supplies power to the processor core and the pll and dll (after ? ltering to become av cc and l2av cc respectively). these columns serve as a reference for the nominal voltage supported on a given signal as selected by the bvsel pin con? guration and the voltage supplied. for actual recommended value of vin or supply voltages see recommended operating conditions. 8. output only for 7410, was i/o for 750/755. 9. enhanced mode only. 10. deasserted (pulled high) at hreset# for 60x bus mode. 11. reuses 750/755 drtry#, dbis#, and tlbisync pins (dti1, dti2, and emode# respectively). 12. unused output in 60x bus mode. 13. connect to hreset# to trigger post power-on-reset (por) internal memory test. 14. ignored in 60x bus mode.
7 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs WED3C7410E16M-XBHX july 2004 rev. 0 preliminary absolute maximum ratings characteristic symbol value unit notes core supply voltage v cc -0.3 to 2.1 v (4) pll supply voltage av cc -0.3 to 2.1 v (4) l2 dll supply voltage l2av cc -0.3 to 2.1 v (4) 60x bus supply voltage ov cc -0.3 to 3.465 v (3) l2 bus supply voltage l2ov cc -0.3 to 2.6 v (3) l2 supply voltage l2v cc -0.3 to 4.6 v (5) input supply processor bus v in -0.3 to 0v cc +0.2 v (2) l2 bus v in -0.3 to l20v cc +0.2 v (2) jtag signals v in -0.3 to ov cc +0.2 v (2) storage temperature range t stg -55 to 150 c notes: 1. functional and tested operating conditions are given in operating conditions table. absolute maximum ratings are stress rat ings only, and functional operation at the maximums is not guaranteed. stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. caution: vin must not exceed ov cc by more than 0.2v at any time including during power-on reset. 3. caution: ov cc /l2ov cc must not exceed v cc /av cc /l2av cc by more than 2.0 v at any time including during power-on reset. 4. caution: v cc /av cc /l2av cc must not exceed l2ov cc /ov cc by more than 0.4 v at any time including during power-on reset. 5. l2ov cc should never exceed l2v cc recommended operating conditions characteristic symbol recommended value unit core supply voltage v cc 1.8v 100mv v pll supply voltage av cc 1.8v 100mv v l2 dll supply voltage l2av cc 1.8v 100mv v memory core supply voltage l2v cc 3.3v 165mv v processor bus supply voltage bvsel = 0 ov cc 1.8 100mv v bvsel = hreset# ov cc 2.5v 100mv v bvsel = hreset or bvsel = 1 ov cc 3.3v 165 mv v l2 bus supply voltage l2vsel = hreset# or 1 l20v cc 2.5v 100 mv v input voltage processor bus and jtag signals vin gnd to ov cc v note: these are the recommended and tested operating conditions. proper device operation outside of these conditions is not gu aranteed
8 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs WED3C7410E16M-XBHX july 2004 rev. 0 preliminary power consumption v cc = av cc = 1.8 0.1v v dc , l2v cc = 3.3v 5% v dc , gnd = 0 v dc , 0 t j < 105c processor (cpu) frequency/l2 frequency unit notes 400mhz/200mhz 450mhz/200mhz full-on mode typical 5.7 6.2 w 1, 3 maximum 13.1 14.3 w 1, 2 doze mode maximum 5.3 5.8 w 1, 2 nap mode maximum 2.25 2.4 w 1, 2 sleep mode maximum 2.20 2.35 w 1, 2 sleep modeCpll and dll disabled maximum 2.0 2.0 w 1, 2 notes: 1. these values apply for all valid system bus and l2 bus ratios. the values do not include ov cc ; av cc and l2av cc suppling power. ov cc power is system dependent, but is typically <10% of v cc power. worst case power consumption, for av cc = 15mw and l2av cc = 15mw. 2. maximum power is measured at v cc = 1.9 v while running an entirely cache-resident, contrived sequence of instructions which keep the execution units maximally b usy. 3. typical power is an average value measured at v cc = av cc = l2av cc = 1.8v, ov cc d = l2ov cc = 2.5v in a system, executing typical applications and benchmark sequences. l2 cache control register (l2cr) the l2 cache control register, shown in figure 5, is a supervisor-level, implementation-speci? c spr used to con? gure and operate the l2 cache. it is cleared by hard reset or power-on reset. figure 5 C l2 cache control register (l2cr) the l2cr bits are described in table 1. l2e l2siz l2clk l2ram l21 l2oh 0000000 0 1 2 3 4 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 22 24 30 31 l2ip l2pe l2do l2ctl l2ts l2sl l2byp l2hwf l2io l2dro l2wt l2df l2fa l2clkstp
9 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs WED3C7410E16M-XBHX july 2004 rev. 0 preliminary table 1: l2cr bit settings bit name function 0 l2e l2 enable. enables l2 cache operation (including snooping) starting with the next transaction the l2 cache unit receives. before enabling the l2 cache, the l2 clock must be con? gured through l2cr[2clk], and the l2 dll must stabilize. all other l2cr bits must be set appropriately. the l2 cache may need to be invalidated globally. 1 l2pe l2 data parity checking enable. enables parity generation and checking for the l2 data ram interface. when disabled, gener ated parity is always zeros. l2 parity is supported by wedcs WED3C7410E16M-XBHX, but is dependent on application. 2C3 l2siz l2 sizeshould be set according to the size of the private memory setting. total sram space is 2m bytes (256kx72). see l2 cache/ private memory con? gurations table in motorola users manual. 4C6 l2clk l2 clock ratio (core-to-l2 frequency divider). speci? es the clock divider ratio based from the core clock frequency th at the l2 data ram interface is to operate at. when these bits are cleared, the l2 clock is stopped and the on-chip dll for the l2 interface i s disabled. for nonzero values, the processor generates the l2 clock and the on-chip dll is enabled. after the l2 clock ratio is chosen, the dll must stabilize before the l2 interface can be enabled. the resulting l2 clock frequency cannot be slower than t he clock frequency of the 60x bus interface. 000 l2 clock and dll disabled 001 1 010 1.5 011 3.5 100 2 101 2.5 110 3 111 4 7C8 l2ram l2 ram typecon? gures the l2 ram interface for the type of synchronous srams used: ? pipelined (register-register) synchronous burst srams that clock addresses in and clock data out the 7410 does not burst data into the l2 cache, it generates an address for each access. 10: pipelined (register-register) synchronous burst sram - setting for WED3C7410E16M-XBHX 9 l2do l2 data only. setting this bit enablesdata-only operation in the l2 cache. when this bit is set, only transactions from t he l1 data cache can be cached in the l2 cache. l1 instruction cache operations will be serviced for instruction addresses already in the l2 cache; however, the l2 cache will not be reloaded for l1 instruction cache misses. note that setting both l2do and l2io effecti vely locks the l2 cache. 10 l2i l2 global invalidate. setting l2i invalidates the l2 cache globally by clearing the l2 status bits. this bit must not be s et while the l2 cache is enabled. see motorolas user manual for l2 invalidation procedure. 11 l2ctl l2 ram control (zz enable). setting l2ctl enables the automatic operation of the l2zz (low-power mode) signal for cache rams. sleep mode is supported by the WED3C7410E16M-XBHX . while l2ctl is asserted, l2zz asserts automatically when the device enters nap or sleep mode and negates automatically when the device exits nap or sleep mode. this bit should not be set when the device is in nap mode and snooping is to be performed through deassertion of qack. 12 l2wt l2 write-through. setting l2wt selects write-through mode (rather than the default write-back mode) so all writes to the l2 cache also write through to the system bus. for these writes, the l2 cache entry is always marked as clean (value unmodi? ed) rather than dirty (value modi? ed). this bit must never be asserted after the l2 cache has been enabled as previously-modi? ed lines can ge t remarked as clean (value unmodi? ed) during normal operation. 13 l2ts l2 test support. setting l2ts causes cache block pushes from the l1 data cache that result from dcbf and dcbst instructions to be written only into the l2 cache and marked valid, rather than being written only to the system bus and marked invalid in the l2 cache in case of hit. this bit allows a dcb z/ dcbf instruction sequence to be used with the l1 cache enabled to easily initialize the l2 cache with any address and data information. this bit also keeps dcbz instructions from being broadcast on the system and single-beat cacheable store misses in the l2 from being written to the system bus. 14C15 l2oh l2 output hold. these bits con? gure output hold time for address, data, and control signals driven to the l2 data ram s. 01: 0.8ns hold time - setting for WED3C7410E16M-XBHX
10 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs WED3C7410E16M-XBHX july 2004 rev. 0 preliminary bit name function 16 l2sl l2 dll slow. setting l2sl increases the delay of each tap of the dll delay line. it is intended to increase the delay thr ough the dll to accommodate slower l2 ram bus frequencies. 0: setting for WED3C7410E16M-XBHX because l2 ram interface is operated above 100 mhz. 17 l2df l2 differential clock. this mode supports the differential clock requirements of late-write srams. 0: setting for WED3C7410E16M-XBHX because late-write srams are not used. 18 l2byp l2 dll bypass is reserved. 0: setting for WED3C7410E16M-XBHX 19 l2fa l2 ? ush assist (for software ? ush). when this bit is negated, all lines castout from the dl1 which have a state of cdmr sv=01xxx1 (i.e. c-bit negated), will not allocate in the l2 if they miss. asserting this bit forces every castout from the dl1 to allocat e an entry in the l2 if that castout misses in the l2 regardless of the state of the c-bit. the l2fa bit must be set and the l2io bit must be cleared in order to use the software ? ush algorithm. 20 l2hwf l2 hardware ? ush. when the processor detects the value of l2hwf set to 1, the l2 will begin a hardware ? ush. the ? ush will be done by starting with low cache indices and increment these indices for way 0 of the cache, one index at a time until the maxim um index value is obtained. then, the index will be cleared to zero and the same process is repeated for way 1 of the cache. for e ach index and way of the cache, the processor will generate a castout operation to the system bus for all modi? ed 32-byte sectors. at the end of the hardware ? ush, all lines in the l2 tag will be invalidated. during the ? ush, all memory activity from the icac he and dcache are blocked from accessing the l2 until the ? ush is complete. snoops, however, are fully serviced by the l2 during the ? ush. when the l2 tags have been fully ? ushed of all valid entries, this bit will be reset to b0" by hardware. when this bit is cle ared, it does not necessarily guarantee that all lines form the l2 have been written completely to the system interface. l2 copybacks ca n stll be queued in the bus interface unit. below is the code which must be run to use l2 hardware flush. when the ? nal sync complete s, all modi? ed lines in the l2 will have been written to the system address bus. disable interrupts dssall sync set l2hwf sync 21 l2io l2 instruction-only. setting this bit enales instruction-only operation in the l2 cache. for this operation, only transac tions from the l1 instruction cache are allowed to be reloaded in the l2 cache. data addresses already in the cache will still hit for the l1 data cache. when both l2do and l2io are asserted, the l2 cache is effectively locked. 22 l2clkstp l2 clock stop. setting this bit enables the automatic stopping of the l2clk_out signals for cache rams that support t his function. while l2clkstp is set, the l2clk_out signals will automatically be stopped when WED3C7410E16M-XBHX enters nap or sleep mode, and automatically restarted when WED3C7410E16M-XBHX exits nap or sleep. 23 l2dro l2 dll rollover. setting this bit enables a potential rollover (or actual rollover) condition of the dll to cause a chec kstop for the processor. a potential rollover condition occurs when the dll is selecting the last tap of the delay line, and thus may risk ro lling over to the ? rst tap with one adjustment while in the process of keeping synchronized. such a condition is improper operation for t he dll, and, while this condition is not expected, it allows detection for added security. this bit can be set when the dll is ? r st enabled (set with the l2clk bits) to detect rollover during initial synchronization. it could also be set when the l2 cache is enabled (with l2e bit) after the dll has achieved its initial lock. 24C30 - reserved 31 l2ip l2 global invalidate in progress (read only)see the motorola users manual for l2 invalidation procedure. table 1: l2cr bit settings
11 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs WED3C7410E16M-XBHX july 2004 rev. 0 preliminary the av cc and l2av cc power signals are provided on the WED3C7410E16M-XBHX to provide power to the clock generation phase-locked loop and l2 cache delay-locked loop respectively. to ensure stability of the internal clock, the power supplied to the av cc input signal should be ? ltered of any noise in the 500khz to 10 mhz resonant frequency range of the pll. a circuit similar to the one shown in figure 6 using surface mount capacitors with minimum effective series inductance (esl) is recommended. multiple small capacitors of equal value are recommended over a single large value capacitor. pll power supply filtering figure 6 C power supply filter circuit av cc (or l2av cc ) 2.2 f 2.2 f gnd low esl surface mount capacitors v cc 10 ? the circuit should be placed as close as possible to the av cc pin to minimize noise coupled from nearby circuits. an identical but separate circuit should be placed as close as possible to the l2av cc pin. it is often possible to route directly from the capacitors to the av cc pin, which is on the periphery of the 255 bga footprint, without the inductance of vias. the l2av cc pin may be more dif? cult to route but is proportionately less critical.
12 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs WED3C7410E16M-XBHX july 2004 rev. 0 preliminary hitce? 255 ball grid array - bh package (63pb/37sn solder balls) notes: 1. dimensions in millimeters and paranthetically in inches. 2. a1 corner is designated with a ball missing the array. t r p n m l k j h g f e d c b a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 bottom view top view 2.50 (0.098) 0.762 (0.030) bsc 0.61 (0.024) bsc
13 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs WED3C7410E16M-XBHX july 2004 rev. 0 preliminary hitce? 255 ball grid array - bh9 package (90pb/10sn solder balls) notes: 1. dimensions in millimeters and paranthetically in inches. 2. a1 corner is designated with a ball missing the array. t r p n m l k j h g f e d c b a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 bottom view top view 2.50 (0.098) 0.762 (0.030) bsc 0.762 (0.030) bsc
14 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs WED3C7410E16M-XBHX july 2004 rev. 0 preliminary powerpc ? is a trademark of international business machine corp. hitce? is a trademark of kyocera corp. ordering information ceramic item unit al 2 o 3 hitce? color black green electrical dielectric constant (1mhz/10ghz) 9.8 5.3/5.2 thermal coef? cient of linear thermal expansion (40~400 degrees c) 1/degree c (x10 -6 ) 7.1 12.3 thermal conductivity (20 degrees c) w / m?k 14 2 mechanical flexural strength mpa 400 175 youngs modulus of elasticity gpa 310 75 hitce? material properties wed 3 c 7410e 16m x bh x x device grade: m = military screened -55c to +125c i = industrial -40c to +85c c = commercial 0c to +70c option: blank = 63pb/37sn solder balls 9 = 90pb/10sn solder balls package type: bh = 255 hitce? ball grid array core frequency (mhz) 400 = 400mhz 450 = 450mhz l2 cache density: 16mbits = 256k x 72 ssram C 200mhz powerpc? type: type 7410e c = multichip package 3 = powerpc? white electronic designs corp.
15 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs WED3C7410E16M-XBHX july 2004 rev. 0 preliminary document title 7410e risc microprocessor hitce? multichip package revision history rev # history release date status rev 0 initial release august 2004 preliminary

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